Project Statistics |
PROP_CompxlibOverwriteLib=true |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PropSpecInProjFile=Store non-default values only |
PROP_SelectedInstanceHierarchicalPath=/testbencg_of_timecode |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2011-07-27T14:45:44 |
PROP_intWbtProjectID=C4A2BBF91AF441079A930D3E173AC0E0 |
PROP_intWbtProjectIteration=4 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.testbencg_of_timecode |
PROP_selectedSimRootSourceNode_par=work.testbencg_of_timecode |
PROP_selectedSimSourceNode=uut_a |
PROP_xilxPostTrceRpt=Error Report |
PROP_AutoTop=false |
PROP_DevFamily=Spartan3 |
PROP_DevDevice=xc3s1000 |
PROP_DevFamilyPMName=spartan3 |
PROP_ISimSimulationRunTime_behav_tb=300 us |
PROP_ISimSimulationRunTime_par_tb=10000 ns |
PROP_DevPackage=ft256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
PROP_netgenRenameTopLevEntTo=spw_fpga_dio |
FILE_UCF=1 |
FILE_VHDL=10 |