spw_digital_io_spwfpga Project Status
Project File: spw_digital_io_spwfpga.ise Current State: Translated
Module Name: spw_fpga_dio
  • Errors:
No Errors
Target Device: xc3s1000-4ft256
  • Warnings:
211 Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
spw_digital_io_spwfpga Partition Summary [-]
No partition information was found.
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 450 7680 5%
Number of Slice Flip Flops 512 15360 3%
Number of 4 input LUTs 681 15360 4%
Number of bonded IOBs 56 173 32%
Number of BRAMs 2 24 8%
Number of GCLKs 6 8 75%
Number of DCMs 1 4 25%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent‰Î 3 31 16:25:07 20090100 Warnings33 Infos
Translation ReportCurrent‰Î 3 31 16:25:27 20090111 Warnings0
Map ReportOut of Date‹à 1 9 19:53:52 2009095 Warnings5 Infos
Place and Route ReportOut of Date‹à 1 9 19:55:56 2009039 Warnings2 Infos
Static Timing ReportOut of Date‹à 1 9 19:56:00 2009002 Infos
Bitgen ReportOut of Date‹à 1 9 19:56:08 2009070 Warnings2 Infos

Date Generated: 05/07/2009 - 18:58:42
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