Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.6 (WebPack) - P.68d Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s1000
Project ID (random number) eb2d7b3239cb49d6bf8dd56ef89a9ff3.C4A2BBF91AF441079A930D3E173AC0E0.4 Target Package: ft256
Registration ID 210777683_0_0_832 Target Speed: -4
Date Generated 2013-08-09T04:13:40 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2760QM CPU @ 2.40GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=8
  • 32-bit adder=1
  • 4-bit adder=1
  • 4-bit subtractor=1
  • 6-bit adder=3
  • 7-bit adder=1
  • 8-bit adder=1
Comparators=12
  • 11-bit comparator less=1
  • 12-bit comparator less=1
  • 32-bit comparator less=4
  • 6-bit comparator equal=3
  • 6-bit comparator greater=1
  • 8-bit comparator greater=1
  • 9-bit comparator less=1
Counters=6
  • 10-bit up counter=1
  • 11-bit up counter=1
  • 32-bit up counter=1
  • 6-bit down counter=1
  • 6-bit up counter=1
  • 7-bit down counter=1
FSMs=4 Multiplexers=1
  • 32-bit 4-to-1 multiplexer=1
Registers=252
  • Flip-Flops=252
Xors=5
  • 1-bit xor2=5
MiscellaneousStatistics
  • AGG_BONDED_IO=70
  • AGG_IO=70
  • AGG_SLICE=423
  • NUM_4_INPUT_LUT=600
  • NUM_BONDED_IOB=70
  • NUM_BUFGMUX=4
  • NUM_CYMUX=144
  • NUM_DCM=1
  • NUM_LUT_RT=79
  • NUM_RAMB16=1
  • NUM_SHIFT=1
  • NUM_SLICEL=422
  • NUM_SLICEM=1
  • NUM_SLICE_FF=400
  • NUM_XOR=106
  • Xilinx Core fifo_generator_v4_1, Coregen 9.2.03i_ip1=2
NetStatistics
  • NumNets_Active=905
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=6
  • NumNodesOfType_Active_CLKPIN=279
  • NumNodesOfType_Active_CNTRLPIN=365
  • NumNodesOfType_Active_DOUBLE=1004
  • NumNodesOfType_Active_DUMMY=1794
  • NumNodesOfType_Active_DUMMYBANK=6
  • NumNodesOfType_Active_DUMMYESC=14
  • NumNodesOfType_Active_GLOBAL=99
  • NumNodesOfType_Active_HFULLHEX=16
  • NumNodesOfType_Active_HLONG=3
  • NumNodesOfType_Active_HUNIHEX=75
  • NumNodesOfType_Active_INPUT=2028
  • NumNodesOfType_Active_IOBOUTPUT=14
  • NumNodesOfType_Active_OMUX=863
  • NumNodesOfType_Active_OUTPUT=788
  • NumNodesOfType_Active_PREBXBY=530
  • NumNodesOfType_Active_VFULLHEX=75
  • NumNodesOfType_Active_VLONG=24
  • NumNodesOfType_Active_VUNIHEX=72
  • NumNodesOfType_Gnd_BRAMADDR=12
  • NumNodesOfType_Gnd_BRAMDUMMY=36
  • NumNodesOfType_Gnd_CNTRLPIN=15
  • NumNodesOfType_Gnd_DOUBLE=10
  • NumNodesOfType_Gnd_DUMMY=1
  • NumNodesOfType_Gnd_DUMMYBANK=8
  • NumNodesOfType_Gnd_INPUT=55
  • NumNodesOfType_Gnd_OMUX=17
  • NumNodesOfType_Gnd_OUTPUT=14
  • NumNodesOfType_Gnd_PREBXBY=17
SiteStatistics
  • IOB-DIFFM=32
  • IOB-DIFFS=29
  • SLICEL-SLICEM=225
SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=1
  • DCM_DCM=1
  • IOB=70
  • IOB_INBUF=49
  • IOB_OUTBUF=21
  • IOB_PAD=70
  • RAMB16=1
  • RAMB16_RAMB16=1
  • RAMB16_RAMB16A=1
  • RAMB16_RAMB16B=1
  • SLICEL=422
  • SLICEL_C1VDD=9
  • SLICEL_C2VDD=15
  • SLICEL_CYMUXF=76
  • SLICEL_CYMUXG=68
  • SLICEL_F=298
  • SLICEL_F5MUX=24
  • SLICEL_FFX=187
  • SLICEL_FFY=212
  • SLICEL_G=301
  • SLICEL_GNDF=59
  • SLICEL_GNDG=47
  • SLICEL_XORF=54
  • SLICEL_XORG=52
  • SLICEM=1
  • SLICEM_FFY=1
  • SLICEM_G=1
  • SLICEM_WSGEN=1
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
DCM
  • PSCLK=[PSCLK_INV:1] [PSCLK:0]
  • PSEN=[PSEN_INV:1] [PSEN:0]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:1]
  • RST=[RST:0] [RST_INV:1]
DCM_DCM
  • CLKDV_DIVIDE=[2:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[8:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:1] [PSCLK:0]
  • PSEN=[PSEN_INV:1] [PSEN:0]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:1]
  • RST=[RST:0] [RST_INV:1]
IOB
  • O1=[O1_INV:0] [O1:21]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:21]
IOB_PAD
  • DRIVEATTRBOX=[12:21]
  • IOATTRBOX=[LVCMOS33:70]
  • PULL=[PULLUP:45]
  • SLEW=[SLOW:21]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEA=[WEA:1] [WEA_INV:0]
  • WEB=[WEB:1] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • PORTA_ATTR=[512X36:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA=[WEA:1] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:1]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • PORTB_ATTR=[512X36:1]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEB=[WEB:1] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:1]
SLICEL
  • BX=[BX_INV:3] [BX:92]
  • BY=[BY:98] [BY_INV:8]
  • CE=[CE:133] [CE_INV:16]
  • CIN=[CIN_INV:0] [CIN:66]
  • CLK=[CLK:274] [CLK_INV:0]
  • SR=[SR:130] [SR_INV:78]
SLICEL_CYMUXF
  • 0=[0:76] [0_INV:0]
  • 1=[1_INV:0] [1:76]
SLICEL_CYMUXG
  • 0=[0:68] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:24] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:88] [CE_INV:16]
  • CK=[CK:187] [CK_INV:0]
  • D=[D:184] [D_INV:3]
  • FFX_INIT_ATTR=[INIT0:178] [INIT1:9]
  • FFX_SR_ATTR=[SRLOW:174] [SRHIGH:13]
  • LATCH_OR_FF=[FF:187]
  • SR=[SR:83] [SR_INV:53]
  • SYNC_ATTR=[ASYNC:183] [SYNC:4]
SLICEL_FFY
  • CE=[CE:103] [CE_INV:16]
  • CK=[CK:212] [CK_INV:0]
  • D=[D:204] [D_INV:8]
  • FFY_INIT_ATTR=[INIT0:203] [INIT1:9]
  • FFY_SR_ATTR=[SRLOW:196] [SRHIGH:16]
  • LATCH_OR_FF=[FF:212]
  • SR=[SR:110] [SR_INV:57]
  • SYNC_ATTR=[ASYNC:207] [SYNC:5]
SLICEL_XORF
  • 1=[1_INV:0] [1:54]
SLICEM
  • BY=[BY:1] [BY_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
SLICEM_FFY
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:1]
  • FFY_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
SLICEM_G
  • DI=[DI:1] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
SLICEM_WSGEN
  • CK=[CK:1] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:1]
  • WE=[WE_INV:0] [WE:1]
 
Pin Data
BUFGMUX
  • I0=4
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
DCM
  • CLK0=1
  • CLK2X=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLK2X=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
IOB
  • I=49
  • O1=21
  • PAD=70
IOB_INBUF
  • IN=49
  • OUT=49
IOB_OUTBUF
  • IN=21
  • OUT=21
IOB_PAD
  • PAD=70
RAMB16
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOB0=1
  • DOB1=1
  • DOB16=1
  • DOB17=1
  • DOB2=1
  • DOB24=1
  • DOB25=1
  • DOB8=1
  • DOB9=1
  • ENA=1
  • ENB=1
  • SSRA=1
  • SSRB=1
  • WEA=1
  • WEB=1
RAMB16_RAMB16
  • ADDRA=1
  • ADDRB=1
  • DIA=1
  • DIB=1
  • DOA=1
  • DOB=1
RAMB16_RAMB16A
  • ADDRA=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DIA=1
  • DOA=1
  • ENA=1
  • SSRA=1
  • WEA=1
RAMB16_RAMB16B
  • ADDRB=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKB=1
  • DIB=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOB=1
  • DOB0=1
  • DOB1=1
  • DOB16=1
  • DOB17=1
  • DOB2=1
  • DOB24=1
  • DOB25=1
  • DOB8=1
  • DOB9=1
  • ENB=1
  • SSRB=1
  • WEB=1
SLICEL
  • BX=95
  • BY=106
  • CE=149
  • CIN=66
  • CLK=274
  • COUT=68
  • F1=295
  • F2=245
  • F3=206
  • F4=160
  • G1=299
  • G2=248
  • G3=198
  • G4=133
  • SR=208
  • X=148
  • XB=2
  • XQ=187
  • Y=152
  • YQ=212
SLICEL_C1VDD
  • 1=9
SLICEL_C2VDD
  • 1=15
SLICEL_CYMUXF
  • 0=76
  • 1=76
  • OUT=76
  • S0=76
SLICEL_CYMUXG
  • 0=68
  • 1=68
  • OUT=68
  • S0=68
SLICEL_F
  • A1=295
  • A2=245
  • A3=206
  • A4=160
  • D=298
SLICEL_F5MUX
  • F=24
  • G=24
  • OUT=24
  • S0=24
SLICEL_FFX
  • CE=104
  • CK=187
  • D=187
  • Q=187
  • SR=136
SLICEL_FFY
  • CE=119
  • CK=212
  • D=212
  • Q=212
  • SR=167
SLICEL_G
  • A1=299
  • A2=248
  • A3=198
  • A4=133
  • D=301
SLICEL_GNDF
  • 0=59
SLICEL_GNDG
  • 0=47
SLICEL_XORF
  • 0=54
  • 1=54
  • O=54
SLICEL_XORG
  • 0=52
  • 1=52
  • O=52
SLICEM
  • BY=1
  • CLK=1
  • G1=1
  • G2=1
  • G3=1
  • G4=1
  • SR=1
  • YQ=1
SLICEM_FFY
  • CK=1
  • D=1
  • Q=1
SLICEM_G
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
  • DI=1
  • WS=1
SLICEM_WSGEN
  • CK=1
  • WE=1
  • WSG=1
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 4 -pcf <fname>.pcf -sdf_anno true -sdf_path <ise_file> -insert_glbl true -insert_pp_buffers true -w -dir netgen/par -ofmt verilog -sim <fname>.ncd <fname>.v
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 10 9 0 0 0 0 0
arwz 3 3 0 0 0 0 0
bitgen 10 10 0 0 0 0 0
map 23 23 0 0 0 0 0
netgen 4 4 0 0 0 0 0
ngc2edif 4 4 0 0 0 0 0
ngdbuild 23 23 0 0 0 0 0
par 24 19 5 0 0 0 0
trce 21 21 0 0 0 0 0
xawinfo 1 1 0 0 0 0 0
xst 31 31 0 0 0 0 0
 
Project Statistics
PROP_CompxlibOverwriteLib=true PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PostTrceFastPath=false PROP_PreTrceFastPath=false
PROP_PropSpecInProjFile=Store non-default values only PROP_SelectedInstanceHierarchicalPath=/testbencg_of_timecode
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-07-27T14:45:44
PROP_intWbtProjectID=C4A2BBF91AF441079A930D3E173AC0E0 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.testbencg_of_timecode PROP_selectedSimRootSourceNode_par=work.testbencg_of_timecode
PROP_selectedSimSourceNode=uut_a PROP_xilxPostTrceRpt=Error Report
PROP_AutoTop=false PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s1000 PROP_DevFamilyPMName=spartan3
PROP_ISimSimulationRunTime_behav_tb=300 us PROP_ISimSimulationRunTime_par_tb=10000 ns
PROP_DevPackage=ft256 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
PROP_netgenRenameTopLevEntTo=spw_fpga_dio FILE_UCF=1
FILE_VHDL=10
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=5 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_FD=28
NGDBUILD_NUM_FDC=204 NGDBUILD_NUM_FDCE=170 NGDBUILD_NUM_FDE=78 NGDBUILD_NUM_FDP=23
NGDBUILD_NUM_FDPE=12 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRE=1 NGDBUILD_NUM_FDS=6
NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=12 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=29
NGDBUILD_NUM_LUT1=77 NGDBUILD_NUM_LUT2=132 NGDBUILD_NUM_LUT2_D=3 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=101 NGDBUILD_NUM_LUT3_D=11 NGDBUILD_NUM_LUT3_L=20 NGDBUILD_NUM_LUT4=292
NGDBUILD_NUM_LUT4_D=12 NGDBUILD_NUM_LUT4_L=18 NGDBUILD_NUM_MUXCY=148 NGDBUILD_NUM_MUXF5=24
NGDBUILD_NUM_OBUF=21 NGDBUILD_NUM_OBUFT=22 NGDBUILD_NUM_RAMB16_S36_S36=2 NGDBUILD_NUM_SRL16=1
NGDBUILD_NUM_VCC=5 NGDBUILD_NUM_XORCY=110
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDC=204
NGDBUILD_NUM_FDCE=170 NGDBUILD_NUM_FDE=78 NGDBUILD_NUM_FDP=23 NGDBUILD_NUM_FDPE=12
NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRE=1 NGDBUILD_NUM_FDS=6 NGDBUILD_NUM_GND=7
NGDBUILD_NUM_IBUF=47 NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=29 NGDBUILD_NUM_LUT1=77
NGDBUILD_NUM_LUT2=132 NGDBUILD_NUM_LUT2_D=3 NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=101
NGDBUILD_NUM_LUT3_D=11 NGDBUILD_NUM_LUT3_L=20 NGDBUILD_NUM_LUT4=292 NGDBUILD_NUM_LUT4_D=12
NGDBUILD_NUM_LUT4_L=18 NGDBUILD_NUM_MUXCY=148 NGDBUILD_NUM_MUXF5=24 NGDBUILD_NUM_OBUF=21
NGDBUILD_NUM_OBUFT=22 NGDBUILD_NUM_PULLUP=45 NGDBUILD_NUM_RAMB16_S36_S36=2 NGDBUILD_NUM_SRLC16E=1
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=7 NGDBUILD_NUM_XORCY=110
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-4-ft256 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=simprims_ver, ieee, vl
Fuse Resource Usage=4086 ms, 61056 KB
Total Signals=59086
Total Nets=38042
Total Blocks=9553
Total Processes=44246
Total Simulation Time=10 us
Simulation Resource Usage=10.4209 sec, 1023168 KB
Simulation Mode=gui
Hardware CoSim=0