spw_fpga_dio Project Status (08/09/2013 - 04:13:50)
Project File: spw_digital_io_spwfpga.xise Parser Errors: No Errors
Module Name: spw_fpga_dio Implementation State: Programming File Generated
Target Device: xc3s1000-4ft256
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
344 Warnings (7 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 1 Failing Constraint
Environment: System Settings
  • Final Timing Score:
631  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 400 15,360 2%  
Number of 4 input LUTs 521 15,360 3%  
Number of occupied Slices 423 7,680 5%  
    Number of Slices containing only related logic 423 423 100%  
    Number of Slices containing unrelated logic 0 423 0%  
Total Number of 4 input LUTs 600 15,360 3%  
    Number used as logic 520      
    Number used as a route-thru 79      
    Number used as Shift registers 1      
Number of bonded IOBs 70 173 40%  
Number of RAMB16s 1 24 4%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 1 4 25%  
Average Fanout of Non-Clock Nets 3.12      
 
Performance Summary [-]
Final Timing Score: 631 (Setup: 631, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent金 8 9 04:13:00 20130102 Warnings (7 new)37 Infos (0 new)
Translation ReportCurrent金 8 9 04:13:06 20130111 Warnings (0 new)2 Infos (0 new)
Map ReportCurrent金 8 9 04:13:10 2013057 Warnings (0 new)5 Infos (0 new)
Place and Route ReportCurrent金 8 9 04:13:21 2013039 Warnings (0 new)0
Static Timing ReportCurrent金 8 9 04:13:24 2013005 Infos (0 new)
Bitgen ReportCurrent金 8 9 04:13:39 2013035 Warnings (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent金 8 9 04:13:40 2013
WebTalk Log FileCurrent金 8 9 04:13:49 2013

Date Generated: 08/09/2013 - 06:30:20